[flashrom] [PATCH] MCP67 SPI detection/debugging

[Carl-Daniel Hailfinger]

First attempt at shedding some light on the MCP67 SPI situation.
Huge thanks to Michael Karcher for reverse engineering the chipset and
writing a spec. Due to this, we were able to use the chinese wall
technique for 100% clean room reverse engineering.

This patch doesn't touch any of the new registers, it only reads them.
Assuming that read has no side effects, this patch is a no-op and safe.

We need "flashrom -V" output from MCP67 boards with SPI flash and from
boards with LPC flash. Note: That output is only helpful if it is
created with patched flashrom and if is from the first run of flashrom
after a cold boot (reset or Ctrl-Alt-Del is not sufficient). I hope to
see a pattern based on which we can detect which flash type is present
on the board.

Alex, we need this output (as described above) from your Asus M2N68-VM
board.

I'd like to merge this ASAP and then ping everyone who had this chipset
to get flashrom -V output.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Index: flashrom-mcp67_spi_detect/chipset_enable.c
===================================================================
--- flashrom-mcp67_spi_detect/chipset_enable.c	(Revision 792)
+++ flashrom-mcp67_spi_detect/chipset_enable.c	(Arbeitskopie)
@@ -1020,6 +1020,76 @@
 	return 0;
 }
 
+/**
+ * The MCP67 code is guesswork based on cleanroom reverse engineering.
+ * Due to that, it only reads info and doesn't change any settings.
+ * It is assumed that LPC chips need the MCP55 code and SPI chips need the
+ * code provided in this function. Until we know for sure, call
+ * enable_flash_mcp55 from this function.
+ */
+static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
+{
+	int result = 0;
+	uint8_t byte;
+	uint16_t status;
+	uint32_t gpiobaraddr;
+	void *gpiobar;
+	struct pci_dev *smbusdev;
+
+	/* dev is the ISA bridge. No idea what the stuff below does. */
+	byte = pci_read_byte(dev, 0x8a);
+	printf_debug("ISA bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5"
+		     " is %i\n", byte, (byte >> 6) & 0x1, (byte >> 5) & 0x1);
+	/* Disable the write code for now until we have more info. */
+#if 0
+	byte |= (1 << 6);
+	byte &= ~(1 << 5);
+	pci_write_byte(dev, 0x8a, byte);
+#endif
+
+	/* Look for the SMBus device. Should we look for the SMBus PCI class? */
+	smbusdev = pci_dev_find(0x10de, 0x0542);
+	if (!smbusdev) {
+		fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
+		exit(1);
+	}
+
+	/* Locate the BAR where the GPIOs live. */
+	gpiobaraddr = pci_read_long(smbusdev, 0x74);
+	printf_debug("GPIO BAR is at 0x%08x, ", gpiobaraddr);
+	/* We hope this has native alignment. We know the GPIOs are at offset
+	 * 0x530, so we expect a size of at least 0x800. Clear the lower bits.
+	 * It is entirely possible that the BAR is 64k big and the low bits are
+	 * reserved for an entirely different purpose.
+	 */
+	gpiobaraddr &= ~0x7ff;
+	printf_debug("after clearing low bits BAR is at 0x%08x\n", gpiobaraddr);
+
+	/* Accessing a NULL pointer BAR is evil. Don't do it. */
+	if (gpiobaraddr) {
+		/* Map the BAR. We access bytewise and wordwise at 0x530. */
+		gpiobar = physmap("MCP67 GPIO", gpiobaraddr, 0x534);
+/* Guessed. If this is correct, migrate to a separate MCP67 SPI driver. */
+#define MCP67_SPI_CS		(1 << 1)
+#define MCP67_SPI_SCK		(1 << 2)
+#define MCP67_SPI_MOSI		(1 << 3)
+#define MCP67_SPI_MISO		(1 << 4)
+#define MCP67_SPI_ENABLE	(1 << 0)
+#define MCP67_SPI_IDLE		(1 << 8)
+		status = mmio_readw(gpiobar + 0x530);
+		printf_debug("SPI control is 0x%04x, enable=%i, idle=%i\n",
+			     status, status & 0x1, (status >> 8) & 0x1);
+		printf("Please send the output of \"flashrom -V\" to "
+		       "flashrom at flashrom.org to help us improve MCP67 chipset"
+		       " support. Thanks.\n");
+	}
+
+	/* Not sure if this is still correct. No docs as usual. */
+	result = enable_flash_mcp55(dev, name);
+
+	return result;
+}
+
 static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
 {
 	uint8_t byte;
@@ -1157,7 +1227,7 @@
 	{0x10de, 0x0365, OK, "NVIDIA", "MCP55",		enable_flash_mcp55}, /* LPC */
 	{0x10de, 0x0366, OK, "NVIDIA", "MCP55",		enable_flash_mcp55}, /* LPC */
 	{0x10de, 0x0367, OK, "NVIDIA", "MCP55",		enable_flash_mcp55}, /* Pro */
-	{0x10de, 0x0548, OK, "NVIDIA", "MCP67",		enable_flash_mcp55},
+	{0x10de, 0x0548, OK, "NVIDIA", "MCP67",		enable_flash_mcp67},
 	{0x1039, 0x0496, NT, "SiS", "85C496+497",	enable_flash_sis85c496},
 	{0x1039, 0x0406, NT, "SiS", "501/5101/5501",	enable_flash_sis501},
 	{0x1039, 0x5511, NT, "SiS", "5511",		enable_flash_sis5511},


-- 
Developer quote of the month: 
"We are juggling too many chainsaws and flaming arrows and tigers."