Difference between revisions of "Random notes"

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(Created page with 'Feel free to cut-n-paste from mails and IRC into this page. Grammar and spelling are not so important. == What numbers do FWH/LPC chips tend to start with? == 39/49/50 with 49 …')
 
m (Dirty little secrets: formatting)
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14:10 < carldani> there's a dirty little secret for EEPROMs
 
14:10 < carldani> there's a dirty little secret for EEPROMs
 +
 
14:10 < carldani> actually, two secrets
 
14:10 < carldani> actually, two secrets
 +
 
14:11 < carldani> 1. old parallel flash chips often need a special board enable or the flash chip will ignore any commands (get ID, erase, write)
 
14:11 < carldani> 1. old parallel flash chips often need a special board enable or the flash chip will ignore any commands (get ID, erase, write)
 +
 
14:11 < carldani> (that's the case with most boards of PIIX4 or older era, flash chip model names are usually *29*)
 
14:11 < carldani> (that's the case with most boards of PIIX4 or older era, flash chip model names are usually *29*)
 +
 
14:12 < carldani> 2. modern chipsets usually have more than one flash bus, and some boards even have additional bus translation chips
 
14:12 < carldani> 2. modern chipsets usually have more than one flash bus, and some boards even have additional bus translation chips
 +
 
14:13 < carldani> so for modern boards you have to check the LPC/FWH bus of the chipset, then you check the SPI bus of the chipset (if supported by the chipset and supported by flashrom), then you check the SPI bus of any LPC-to-SPI bus translation chip
 
14:13 < carldani> so for modern boards you have to check the LPC/FWH bus of the chipset, then you check the SPI bus of the chipset (if supported by the chipset and supported by flashrom), then you check the SPI bus of any LPC-to-SPI bus translation chip
 +
 
14:13 < carldani> on the M2N68, we only probe for LPC chips, but the chip on the board is SPI
 
14:13 < carldani> on the M2N68, we only probe for LPC chips, but the chip on the board is SPI
 +
 
14:14 < carldani> that means the SPI chip is either attached to the SPI bus of the chipset (and we don't have a driver for that due to lack of docs)
 
14:14 < carldani> that means the SPI chip is either attached to the SPI bus of the chipset (and we don't have a driver for that due to lack of docs)
 +
 
14:14 < carldani> or it is behind some LPC/SPI translation chip (some of which we support)
 
14:14 < carldani> or it is behind some LPC/SPI translation chip (some of which we support)
 +
 
14:14 < carldani> the translation test is performed with -p it87spi
 
14:14 < carldani> the translation test is performed with -p it87spi
 +
 
14:15 < carldani> as you can see, it's complicated
 
14:15 < carldani> as you can see, it's complicated
14:15 < carldani> very very complicated
+
 
 
14:15 < carldani> worst of all, autodetection is basically impossible
 
14:15 < carldani> worst of all, autodetection is basically impossible

Revision as of 12:47, 20 August 2009

Feel free to cut-n-paste from mails and IRC into this page. Grammar and spelling are not so important.

What numbers do FWH/LPC chips tend to start with?

39/49/50 with 49 being the most common. I've seen 39/49 chips which are parallel but that's ususual. 50 is not very common as model number.

Dirty little secrets

14:10 < carldani> there's a dirty little secret for EEPROMs

14:10 < carldani> actually, two secrets

14:11 < carldani> 1. old parallel flash chips often need a special board enable or the flash chip will ignore any commands (get ID, erase, write)

14:11 < carldani> (that's the case with most boards of PIIX4 or older era, flash chip model names are usually *29*)

14:12 < carldani> 2. modern chipsets usually have more than one flash bus, and some boards even have additional bus translation chips

14:13 < carldani> so for modern boards you have to check the LPC/FWH bus of the chipset, then you check the SPI bus of the chipset (if supported by the chipset and supported by flashrom), then you check the SPI bus of any LPC-to-SPI bus translation chip

14:13 < carldani> on the M2N68, we only probe for LPC chips, but the chip on the board is SPI

14:14 < carldani> that means the SPI chip is either attached to the SPI bus of the chipset (and we don't have a driver for that due to lack of docs)

14:14 < carldani> or it is behind some LPC/SPI translation chip (some of which we support)

14:14 < carldani> the translation test is performed with -p it87spi

14:15 < carldani> as you can see, it's complicated

14:15 < carldani> worst of all, autodetection is basically impossible