Download & Installation
If you just want to browse the source code, please go to http://code.coreboot.org/p/flashrom/source/tree/HEAD/trunk.
- pciutils development package (pciutils-dev/libpci-dev/pciutils-devel, depending on OS/distribution)
- zlib development package (zlib1g-dev/zlib-devel, depending on OS/distribution)
- subversion (if you checkout the source and build manually)
Manual Installation From Source:
$ svn co svn://coreboot.org/flashrom/trunk flashrom
$ cd flashrom
$ sudo make install
- Debian: sudo aptitude install flashrom
- Fedora: sudo yum install flashrom
- Gentoo: emerge flashrom
- Mandriva: urpmi flashrom
- openSUSE: yast -i coreboot-utils
- T2 SDE
- Installation from source: Emerge-Pkg flashrom
- Installation of binaries: mine -i flashrom-0.9.0.tar.bz2
- FreeBSD: cd /usr/ports/sysutils/flashrom && make install clean
- Windows: There is a Windows port of the flashrom utility. Download the latest version: DarmawanMappatutu_Salihun.tar.gz.
Please see the flashrom(8) manpage.
Fully testing flashrom chip/southbridge/mainboard support
See this page for instructions on how to test flashrom properly (this may be risky, make sure you have a working backup flash chip).
Flashrom Live CD
Flashrom Live CD
Flash chip overview
Modern mainboards store the BIOS in a reprogrammable flash chip. There are hundreds of different flash (EEPROM) chips, with variables such as memory size, speed, communication bus (Parallel, LPC, FWH, SPI) and packaging to name just a few.
Probably the only property of flash chips which is completely irrelevant to flashrom. The three most common packages are called DIP, PLCC and TSOP. The BIOS copyright holders often place a fancy sticker on the BIOS chip showing a name or logo, BIOS version, serial number and copyright notice.
DIP32: Dual In-line Package, 32 pins
A rectangular black plastic block with 16 pins along each of the two longer sides of the package (32 pins in total). DIP32 chips can be socketed which means they are detachable from the mainboard using physical force. Since they haven't been moved in and out of the socket very much (yet, hehe) they can appear to be quite difficult to release from the socket. One way to remove a DIP32 chip from a socket is by prying a thin screwdriver in between the plastic package and the socket, along the shorter sides where there are no pins, and then gently bending the screwdriver to push the chip upwards, away from the mainboard. Alternate between the two sides to avoid bending the pins, and don't touch any of the pins with the screwdriver (see FAQ about ESD, electro-static discharge). If the chip is soldered directly to the mainboard, it has to be desoldered in order to be reprogrammed outside the mainboard. If you do this, it's a good idea to solder a socket to the mainboard instead, to ease any future experiments.
PLCC32: Plastic Leaded Chip Carrier, 32 pins
Black plastic block again, but this one is much more square. PLCC32 was becoming the standard for mainboards after DIP32 chips because of it's smaller physical size. PLCC can also be socketed or soldered directly to the mainboard. Socketed PLCC32 chips can be removed using a special PLCC removal tool', or using a piece of nylon line tied in a loop around the chip and pulled swiftly straight up, or bending/prying using small screwdrivers if one is careful. PLCC32 sockets are often fragile so the screwdriver approach is not recommended. While the nylon line method sounds strange it works well. Desoldering PLCC32 can be painful without specialized desoldering equipment particularly because PLCC32 chips have leads on all four sides of the package, but it's certainly doable.
DIP8: Dual In-line Package, 8 pins
SO8/SOIC8: Small-Outline Integrated Circuit, 8 pins
TSOP: Thin Small-Outline Package
TSOPs are often used in embedded systems where size is important and there is no need for replacement in the field. It is possible to (de)solder TSOPs by hand, but it's not trivial and a reasonable amount of soldering skills are required.
Communication bus protocol
There are four major communication bus protocols for flash chips, each with multiple subtle variants in the command set:
- Parallel: The oldest flash bus, phased out on mainboards around 2002.
- LPC: Low Pin Count, a standard introduced ca. 1998.
- FWH: Firmware Hub, a variant of the LPC standard introduced at the same time. FWH is a special case variant of LPC with one bit set differently in the memory read/write commands. That means some data sheets mention the chips speak LPC although they will not respond to regular LPC read/write cycles.
- SPI: Serial Peripheral Interface, introduced ca. 2006.
Here's an attempt to create a marketing language -> chip type mapping:
- JEDEC Flash -> Parallel (well, mostly)
- FWH -> FWH
- Firmware Hub -> FWH
- LPC Firmware -> FWH
- Firmware Memory -> FWH
- Low Pin Count (if Firmware/FWH is not mentioned) -> LPC
- LPC (if Firmware is not mentioned) -> LPC
- Serial Flash -> SPI
SST data sheets have the following conventions:
- LPC Memory Read -> LPC
- Firmware Memory Read -> FWH
If both are mentioned, the chip supports both.
If you're not sure about whether a device is LPC or FWH, look at the read/write cycle definitions.
||1101 for READ, 1110 for WRITE.
||0000 to 1111
||IDSEL value to be shifted out to the chip.
||The address to be read/written. 7 cycles total == 28 bits.
||010X for READ, 011X for WRITE. X means "reserved".
||The address to be read/written. 8 cycles total == 32 bits.
Generally, a parallel flash chip will not speak any other protocols. SPI flash chips also don't speak any other protocols. LPC flash chips sometimes speak FWH as well and vice versa, but they will not speak any protocols besides LPC/FWH.